Current research is directed towards a greater density of active components per unit area of semiconductor substrate, such that effective isolation between circuits must be installed properly to avoid the short circuiting of adjacent components. There are thermal techniques, such as the local oxidation of silicon (LOCOS), to grow silicon dioxide layers with a thickness more than one thousand angstroms between active devices. The insulating characteristic of silicon dioxide is for isolation purposes and is also called field oxide.
As the size of integrated circuits is reduced, the devices that make up the circuits must be positioned closer together in order to comply with the limited space available on a typical chip. Conventional isolation of circuit components in modern integrated circuit technology takes the form of shallow trenches which are etched into the semiconductor substrate and are filled with an insulating material such as silicon dioxide. These areas are generally referred to as shallow trench isolation (STI). In sub 0.5 microns applications, the use of shallow trench isolation between devices in an integrated circuit wafer is frequently used in place of the LOCOS process. Shallow trench isolation regions serve to isolate the active regions of the integrated circuit and, typically vary widely in dimensions because the active regions of the integrated circuit can be of virtually any size.
In the advanced semiconductor processes, a complex topography of integrated circuits are often encountered. Due to this reason, a problem is always occurs in achieving a uniform shallow trench isolation oxide fill, especially when shallow trenches of widely varying widths are used. In order to solve this problem, a number of methods have been developed for filling shallow trench isolation with insulating materials and for planarizing the topography.
The filling methods of STI include chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD), which take advantage of the fact that material can be evaporated as a vapor and deposited on a surface. PECVD can further improve the stress of the deposited film and reduce the wafer warpage or peeling by the ion bombardment. Planarization methods such as the resist etch back (REB) process, the reactive ion etching (RIE) process, the spin on glass (SOG) method, and the chemical mechanical polishing (CMP) are employed, alone or in combination, to planarize the surface of the semiconductor substrate.
The conventional shallow trench isolation process is strongly dependent on the controllability of chemical mechanical polishing (CMP), which is the only method to provide the global planarization of ultra-large semiconductor integration (ULSI) processes. After the oxide-filled shallow trench isolation is formed, many attempts have been made utilizing CMP processes. One such method is described in U.S. Pat. No. 5,494,857, entitled "CHEMICAL MECHANICAL PLANARIZATION OF SHALLOW TRENCHES IN SEMICONDUCTOR SUBSTRATES" by S. S. Cooperman et al., which applies CMP techniques to etch back the insulating layers and to form shallow trench isolation.
Another method is described in U.S. Pat. No. 5,312,512, entitled "GLOBAL PLANARIZATION USING SOG AND CMP" by Allman, which discusses the global planarization of integrated circuit wafers using Spin On Glass and Chemical Mechanical Polishing processes.
Nevertheless, a plurality of factors includes polishing slurry, pressure on the wafer, polishing pad, particle size distribution of slurry, etc. will affect the CMP planarization profile. A serious drawback for CMP is the difficulty in end point detection. Other weak points are induced from CMP and comprises easy to form microscratches on the polishing surface, bad within wafer uniformity, pattern-dependent polishing uniformity, instability of polishing rate, and contamination control of the wafer.
According to the above descriptions, although CMP can achieve true global planarization on the deposited film, the strong dependence upon CMP of shallow trench isolation may complicate the processes and cause some problems that are not easy to solve.
Summary of the Invention Shallow trench isolation (STI) is now widely used in the ultra-large semiconductor integration (ULSI) industry. Due to the requirement of STI planarization to facilitate the subsequent processes, there are a lot of methods to planarize the STI surface. Chemical mechanical polishing (CMP) procedure dominate the semiconductor planarization processes but will complicate the STI formation and cause some disadvantages such as surface microscratches, polishing uniformity, and unstable polishing rate of the film property. Therefore it is an object of the present invention to provide a method for forming a shallow trench isolation via non-critical chemical mechanical polishing of ULSI processes.
It is another object of the present invention to provide a fully planar surface for an integrated circuit at the conclusion of a shallow trench isolation process.
These objects have been achieved by first forming a pad oxide on a semiconductor substrate, then a silicon nitride formed thereon. Subsequently, the wafer take the first photolithography and etching steps to form a photoresist on the stacked layer and etching the underlying silicon nitride to expose the shallow trench isolation region. After the photoresist is removed, using silicon nitride as a mask to etch the substrate, shallow trench isolation regions are formed therein. After thermal oxidation of the STI regions, depositing a thick layer of dielectric layer to fill the STI regions by using a high density plasma chemical vapor deposition (HDP-CVD) method. The dielectric layer is silicon dioxide (SiO.sub.2) and the HDP oxide is a more stable film than ozone-TEOS, which can fill a narrow trench without any weak spot. Thus, thickness of deposited oxide in shallow trenches is un-conformal and almost independent of trench widths.
After the step of trench filling, a wet etching step is used to etch back the oxide layer. Since the oxide layer is deposited both on the shallow trenches and the silicon nitride layer, the oxide layer formed on the silicon nitride will be etched simultaneously to expose the corner of the silicon nitride. Then a second silicon nitride layer is deposited on STI regions and the first silicon nitride regions (active regions) to act as a cap layer. Afterward, a non-critical photolithography and etching step is used to form a patterned photoresist and expose bigger active areas with a width more than 1 micron meter. Then, the top silicon nitride layers on bigger active areas are removed.
After stripping of the remaining photoresist, a non-critical chemical mechanical polishing step is used to polish the result structure. The purpose of the non-critical CMP process is not for the planarization of the STI regions, but is used to remove the cap layer on smaller active areas. Then, the oxide layer overlaying active areas are wet etched by using dilute HF solution wet dip or BOE. The wet acid solutions have a very slow etching rate on silicon nitride, therefore the active areas under nitride layer and the oxide layer within STI regions will not be affected. After the wet etching step of oxide layer, another wet etching step using hot H.sub.3 PO.sub.4 solution is also employed to strip the remaining first and second silicon nitride layers.
As described in the previous descriptions, a conventional CMP process is also used. Nevertheless, a non-critical photoresist patterning process in combination with a non-critical CMP process are used to ease the production, the drawbacks of critical CMP process controllability for STI planarization to not exist. Thus the integrated shallow trench isolation process is much easier for mass production.